Decoupled Design of Inverter Output Impedance for Parallel Operated Inverters: An Analytical Approach

The concept of microgrid emerged in the early 2000 and initially it was proposed as a means/solution of integrating renewable energy resources. These energy resources are not available round the clock due to their volatile and intermittent nature. Therefore, it was not easy to connect them in large quantities, and consequently, the idea of a microgrid was laid down. However, the renewable energy resources have received a lot of attention in recent years because of their self-renewal nature over the passage of time, deterioration, and depletion of the global environment and energy. The integration of renewable energy based distributed energy resources is demanded by the power system community to achieve the objectives of reliable, economical, and carbon-free supply [1,2]. Most of these resources are interfaced with the utility grid by power electronic based converters. Due to the negligible inertia of power converters, the stability issues in such systems remain a matter of concern. However, maintaining the system stability in the face of fluctuating microgrid operating conditions is also a crucial design problem. The study, which examines the stability issues using a single-phase community microgrid concept, was conducted in [3]. On the other hand, the presence of rotating inertia in the conventional synchronous alternators assists in stabilizing the system via the well-known droop control concept, which originates from the principle of power balance in synchronous machines. An imbalance between the input mechanical power and the output electric power causes a change in the rotor speed and electrical frequency. Similarly, the variation in output reactive power results in voltage magnitude deviation. Such characteristics can be artificially created for an electronically interfaced inverter-based AC microgrid [4].

The mechanisms of active and reactive power regulation through droop control, and their effects on voltage and frequency, have been studied in the past. The form of the droop equations varies depending on the nature of the inverter’s output impedance, which may be resistive, inductive, or capacitive.The output Impedance of the power inverter plays an important/crucial role in improving the quality of the output voltage. Inverter designed with resistive and inductive output impedances have different levels of total harmonic distortion in the output voltage [4,5]. Besides this, inverter output impedance also controls the load sharing accuracy of various VSI units connected in parallel [6]. The parallel operation of inverters becomes important when it comes to the availability of high current power electronic devices, system redundancy, reliability expected by critical customers, etc. The issues of thermal management and design of high power inverters are expected to be alleviated by parallel operation. Therefore, the challenge of sharing the load among parallel operated inverters is required to be addressed well [7].

However, the power converters, which are equipped with the conventional droop controllers to share active as well as reactive power, have inherent limitations of inaccurate sharing of power, circulating current, etc. One such issue in the low voltage dc microgrid is addressed, and its solution is proposed by adaptive droop control that minimizes the difference between circulating currents via a virtual resistor [8]. The presence of a nonlinear load in the conventional control is also a problematic situation as far as the quality of load voltage and grid current waveform is concerned [9]. The intrinsic drawbacks of the typical droop controller include erroneous power sharing to the load as a result of mismatched output impedances between inverters, noise, disturbances, numerical computations, mismatched components, etc. An uncertainty and disturbance estimator based droop control is proposed to address these issues [10]. Various solutions are reported in the literature to address the aforesaid issues in the past. In this order, Ref. [11] presents the limitations of the CDC (conventional droop control) and then modifies the droop control structure in a robust form, thereby avoiding the condition of the same per unit output impedance between parallel inverters. Inverters are classified as inductive, resistive, or capacitive according to the nature of their output impedance, and each type is associated with a corresponding droop control equation[12]. A universal droop control strategy, which adopts the droop control formulation of a resistive inverter, is proposed in [13] for inverters with an output impedance angle ranging from −π/2 to +π/2 radians.The same model of resistive inverter is shown to be stable in the output impedance angle range of −π/2 to +π/2 radians through a small signal stability tool [14]. The parallel operation of inverters with different types of output impedance is made possible by universal droop controllers; however, droop controllers still have to trade-off between power sharing and load voltage and frequency regulation. This trade-off can be somewhat eliminated by the approach suggested in [15].

The various intrinsic features of microgrid are covered in primary, secondary, and tertiary layers of control. The key features of a multilayer control system are regulating reactive and active power flow to maintain stable voltage amplitude and frequency, and adding reactive power compensation, harmonic current sharing, and filtering to ensure disturbance rejection and meet power quality standards in microgrids. A network forming three phase isolated inverter model with its primary controls (droop control) is simulated to illustrate its working [16]. In the hierarchical control of a microgrid, the function of restoring voltage and frequency by the secondary layer of control for two network forming converters is illustrated through a case study [17]. A new data-driven distributed control structure is presented employing a droop-free paradigm for voltage/frequency regulation and reactive/active power sharing of islanded microgrids in order to minimize the inherent temporal gap between primary and secondary control [18]. The concept of replacement of primary and secondary droop control by regulators is proposed in [19]. In the literature discussed above [7,10,11,12,13,14], shaping of the output impedance remains at the center to reduce THD_v, which requires tuning procedures. To eliminate the need for tuning, the concept of smart impedance, which can perform manipulations, is proposed in [20] to perform the tuning procedure electronically.

However, in light of the literature, discussed above, the simplistic didactic approach to understand proportional power sharing to the load and maintaining the power quality simultaneously is still missing. Therefore, keeping this in mind, efforts have been put to achieve the following objectives in a comprehensive manner.

The paper is organized as follows. Section 2 discusses the deterioration mechanism of voltage with its mathematical foundation. Section 3 presents the design of the integrator coefficient for the capacitive inverter, followed by the modified BHC strategy in Section 4 to further improve the output voltage quality. The small signal model of capacitive type inverter is obtained in Section 5 followed by basic stability analysis for the BHC equipped inverter. Section 6 discusses the inherent limitations of CDC and presents a robust droop control (RDC) scheme as a remedial measure to address these limitations. Various scenarios and detailed simulations are discussed in Section 7. Section 8 concludes the paper.

Various renewable energy sources, such as tidal, wind, and solar power, are increasingly being developed. Microgrids are commonly formed using power inverters, which may or may not be connected to the grid. Degradation in the voltage supplied by inverters is a significant power quality issue in these applications [7]. This section focuses on the underlying mechanism behind the degradation of voltage quality.

The output voltage of such an inverter, modeled in Figure 1a, is expressed in Equation (1) by referring its equivalent circuit in Figure 1b.

Where E (volt) and δ (radians) are the magnitude and phase angle of the reference voltage v_r; $${\mathrm{Z}}_{\mathrm{o}}$$ (Ω) and θ (radians) are the magnitude and angle of inverter output impedance; S, P and Q are apparent, active and reactive power; $${\mathrm{V}}_{\mathrm{o}}$$ (volt) is the voltage across the output terminals, and i (amp) is the current flowing through $${\mathrm{Z}}_{\mathrm{o}}$$.

The current i contains harmonics due to the inclusion of nonlinear load or/and the PWM in the inverter, thus causing harmonic voltage drop in the impedance, $${\mathrm{Z}}_{\mathrm{o}}.$$ Harmonic voltage components appearing in the output voltage will degrade the output voltage and induces total harmonic distortion (THD) provided the reference voltage is free of harmonics. THD may also appear in the output voltage due to harmonic components in the voltage reference, $${\mathrm{v}}_{\mathrm{r}}$$. One possible solution to make the output voltage harmonic free, is to keep the reference voltage clean. Additionally, the magnitude of the inverter output impedance should be as small as possible over the range of dominant harmonic frequency components. Another way is to deroute harmonic current components from current i, in order to make it clean. In the third option, the reference voltage ($${\mathrm{v}}_{\mathrm{r}}$$) should provide an adequate amount of harmonic voltages $$\left({\mathrm{v}}_{\mathrm{o}\mathrm{h}}\right)$$ to neutralize the harmonic voltage drops in the output impedance, $${\mathrm{Z}}_{\mathrm{o}}$$.

In this section, the mathematical relationship between the inverter output impedance and THD_v is established. The inverter current i, as shown in Figure 1, can be expressed in terms of its harmonic components as follows.

where h is the harmonic order number. The ω and $${\mathrm{\Phi }}_{h}$$ are angular frequency (radians/s) and h-th phase angle (radians) respectively.

The fundamental component of $${\mathrm{v}}_{\mathrm{o}}$$ is expressed as

assuming that the voltage reference $${\mathrm{v}}_{\mathrm{r}}$$ is clean and sinusoidal, which is expressed in Equation (4).

where

where

and

Now the output voltage harmonic components would be

By referring Equation (8), it is clear that $${\mathrm{v}}_{\mathrm{o}\mathrm{h}}$$ depends upon harmonic current components and impedance at harmonic frequencies. The fundamental component of output voltage, $${\mathrm{v}}_{\mathrm{o}1}$$ is determined by reference voltage, fundamental current and output impedance at fundamental frequency. It is evident from this analysis that $${\mathrm{v}}_{\mathrm{o}\mathrm{h}}$$ is not affected by $${\mathrm{v}}_{\mathrm{o}1}$$ and this feature can be used to design the impedance for different purposes. The output impedance at harmonic frequencies can be reduced for a selected value of virtual capacitance, connected in series with filter inductor, in order to reduce per unit THD of the output voltage, expressed in Equation (9). On the other hand, objective of proportional load sharing is governed by the design of fundamental output impedance. Therefore, the optimum design of a virtual capacitor at high harmonic frequencies decouples to meet the requirements of proportional load sharing and low THD_v [7].

In order to further analyse the source of harmonics in the output voltage and its mitigation measures, the circuit model of Figure 1b is redrawn in Figure 2 for a particular h-th harmonic component. The following set of equations are written by referring Figure 2a.

and,

The superposition theorem allows us to decompose this circuit into multiple h-th order circuits for analysis purposes. The circuit shown in Figure 2b is the h-th order decomposed circuit. If $${\mathrm{v}}_{\mathrm{o}h}$$ = 0, then only the current source is left in the right part of the circuit, shown in Figure 2b. Ideally, the function of an inverter should be to supply power at the right voltage and frequency as per standards/laws. If multiple inverters are working in conjunction, the proportional sharing of power is also required at the fundamental frequency. The harmonics in the output voltage should ideally be zero, i.e., $${\mathrm{v}}_{\mathrm{o}h}$$ = 0. (h = 2, 3, …) even if the presence of $${i}_{h}$$ exists. This can be accomplished only when the drop of h-th order current on the output impedance is equal to h-th order component of the reference voltage.

The application of this concept can facilitate the design of a controller to reduce THD_v.

The objective of designing the capacitive type inverter is to reduce the magnitude of output impedance at dominating harmonic frequency components (h = 3, 5, ...), thereby reducing the THD of load or output voltage, in the case of a nonlinear load. The single phase H-bridge insulated gate bipolar transistor (IGBT) inverter circuit with its control circuitry, as shown in Figure 3, is under consideration for designing the capacitive output impedance. The inverter is connected to an AC bus through a switch, where the load is assumed to be connected. The current i (current in the filter inductor) can be passed through an integrator block to make the output impedance capacitive, as shown in the closed-loop system in Figure 4 [12].

By referring Figure 3 and Figure 4, the following relationships are expressed in Equation (14).

Since the average of $${\mathrm{u}}_{\mathrm{f}}$$ over a switching period can be approximated by u [7]. Therefore, equating both terms in Equation (14) yields

where,

Now, output impedance, denoted by $${\mathrm{Z}}_{\mathrm{o}}\left(\mathrm{s}\right),$$ is expressed as follows

Neglecting the parasitic resistance, r (usually small)

At the fundamental frequency, the output impedance can be made almost entirely capacitive if the capacitance $${\mathrm{C}}_{\mathrm{o}}$$ is small enough to negate the effect of an inductor. Due to the presence of an integrator block, any dc offset in the current i, e.g., that caused by the conversion process or faults in the system, would lead to a dc component in the reference signal and hence in the load voltage. In order to avoid this problem, two solutions are presented.

To derive the condition for system stability, we will use the conventional control-system approach. If the controller is implemented digitally, the effect of sampling, PWM conversion, and computation can be approximated by a step delay $${e}^{-s{T}_{s}}$$, where $${T}_{s}$$ is the sampling period. The block diagram of the current loop (Figure 5) is shown below [7].

The corresponding open loop transfer function is given by

The open loop transfer function has a pole at s = 0, and there is no pole in the right half of the s plane. Here, the Nyquist plot tool of the control system is used to ensure the stability of the open loop transfer function. According to the condition of stability, in the Nyquist method, the plot should not encircle the critical point (−1, 0) on the real axis of the s-plane. If the plot crosses the real axis for the first time at some frequency $${\omega }_{o}$$, then

Therefore, $$\mathrm{tan}\left({\omega }_{o}{T}_{s}\right)$$ = $$\frac{r}{{\omega }_{o}\mathrm{L}}$$

The loop gain is given by:

The loop gain should be less than 1 at this frequency $${\omega }_{o}$$, or otherwise, the loop is stable if

where 0 < $${\omega }_{o}$$ < $$\frac{\pi }{2{T}_{s}}$$

Therefore, the loop shown in Figure 4 is stable if

For a small parasitic resistor r, the right hand side of the above equation reduces to $${\left(\frac{\pi }{2{T}_{s}}\right)}^{2}$$L. The loop will be stable if capacitor $${\mathrm{C}}_{\mathrm{o}}$$ or the switching frequency, $${f}_{s}$$ = $$\frac{1}{{T}_{s}}$$ is chosen large enough so that the sampling frequency $${f}_{s}$$ is larger than four times of $$\frac{1}{2\pi \sqrt{\mathrm{L}{\mathrm{C}}_{\mathrm{o}}}}$$. Also, in practicality, r is not zero, which assists in maintaining stability.

As discussed previously in Section 2.1, the THD of the voltage is governed by the inverter output impedance at the harmonic frequencies. In order to make the output impedance capacitive in nature and reduce its magnitude at dominating harmonic frequencies, a virtual capacitance is added in series with the filter inductor. The procedure of obtaining the optimum design of $${\mathrm{C}}_{\mathrm{o}}$$ or integrator constant is described below.

The minimization problem can be solved by taking the derivative of the function and then equating it to zero,

By referring the expression in Equation (9), THD_v can be reduced by minimizing the harmonic voltage drops on the output impedance. Therefore,

The magnitude of the output impedance at $$h$$-th harmonic frequency is expressed in (24) by considering virtual capacitance $${\mathrm{C}}_{\mathrm{o}}$$.

where

h and $${\mathrm{\omega }}^{*}$$ are harmonic order and fundamental frequency, respectively. The parasitic resistance, r can be neglected as it has a small value. Minimization of the function f ensures improved THDv for a particular virtual capacitor$$\,{\mathrm{C}}_{\mathrm{o}}$$. Differentiating Equation (23) with respect to $${\mathrm{C}}_{\mathrm{o}}$$ and equating to zero yields the optimum capacitance, expressed in Equation (25).

where,$$\,\mathrm{ }{i}_{1h}$$ = $$\frac{{\mathrm{I}}_{h}}{{\mathrm{I}}_{1}}$$, is h-th order normalized harmonic current with respect to fundamental current.

Substituting $${\mathrm{C}}_{\mathrm{o}}$$ in Equation (23) yields the following

It is evident from the above equation that THD is proportional to the inductance L. A small L not only reduces the inductor size and cost, but also it enables a small integrator gain to ensure the stability of the current loop. Assuming odd harmonics (h = 3, 5, 7, …) are equally distributed, Equation (25) will have the form

Assuming the 3rd, 5th, and 7th harmonic components, the optimal capacitance, which is calculated by using Equation (27), is given by

The optimal capacitance values, designed for specific harmonic frequencies, are listed in Table 1. The fundamental inverter output impedance $$(Z_o)$$ are too illustrated. The plot of output impedance gain with respect to frequency (Hz) for optimal capacitance (designed for h = 3rd and 5th) is shown in Figure 6b. The output impedance gain at the fundamental frequency is negative and goes from negative to positive at 1142 rad/s.

The suggested method enables the first order design of an integrator for specific harmonic frequency components. Though it is possible to build a topology of an integrator with a higher order, that is not discussed here due to page limitations.

Besides low THD in the output voltage, the proportional load sharing between inverters is also recommended. The idea of a robust droop controller arises as the conditions for achieving the aforesaid objectives in the conventional counterpart are not met in practice. In this sub section, the conditions required for proportional load sharing using conventional droop controllers are first derived, followed by a discussion of the robust droop control scheme. The circuit models of two inverters, shown in Figure 6a, with capacitive output impedances, are connected in parallel. The feeder impedance is neglected, and the inverter output impedance dominates between the inverter and the AC bus [11,14].

By referring Figure 1b, the expression of apparent power can be written as

where $${\mathrm{v}}_{\mathrm{o}}$$ and I are the RMS values of output voltage and current, respectively. The active and reactive power outputs are expressed as

For the capacitive output impedance of the inverter, θ = −90°. With this substitution, the active and reactive power of i-th inverter are expressed in Equation (32) and Equation (33).

For a very small angle δ, $${\mathrm{P}}_{i}$$~ −δ & $${\mathrm{Q}}_{i}$$~ −E; i being the number of inverters participating in the parallel operation.

Therefore, the conventional droop control characteristics for capacitive inverters are shown in Equation (34). The corresponding characteristics are shown in Figure 7.

Substituting Equation (34) into Equation (33), the expression of the reactive power of i-th inverter is written as follows

Substituting Equation (35) into Equation (34), the deviation in voltage amplitude between two inverters is given by

Voltage deviation between two units leads to considerable error in power sharing. Therefore, in order for $${\mathrm{n}}_{1\mathrm{C}}{\mathrm{Q}}_{1}$$ = $${\mathrm{n}}_{2\mathrm{C}}{\mathrm{Q}}_{2}$$ to hold, the voltage deviation should be zero. However, this condition is not obeyed in practicality. It is satisfied if

Therefore, in order to obtain accurate reactive power sharing, capacitive output impedance, $${Z}_{o}$$ should be designed to satisfy the condition stated in Equation (38)

or

where$$\,{S}_{1}$$, $${S}_{2}$$, …, $${S}_{n}$$ are inverter ratings in volt amperes. By referring to Equation (39), it is evident that for achieving accurate reactive power sharing, the p.u. output impedances of inverters should be the same, and this is the foundation of the approach known as virtual impedance. However, it is difficult to achieve this in a real scenario [7,14]. In the same way, it can be shown that real power sharing can be ensured under the condition of $$\frac{{\mathrm{Z}}_{02}}{{\mathrm{Z}}_{01}}$$ = $$\frac{{m}_{2C}}{{m}_{1C}}$$.

As stated in Section 3.2.1, the conventional droop control strategy may not able to share power accurately due to the lack of a mechanism to ensure that voltage set points are the same under disturbance, noise, etc. [7,11,14]. This issue can be resolved through bolting a voltage regulator onto the conventional droop controller (CDC), as shown in Figure 8.

At the steady state, input to the integrator is zero.

If $$\mathrm{{K}_{e}}$$ is same for all inverters that are operating in parallel, an accurate reactive power sharing is guaranteed in proportion to the power rating of the inverters.

By referring Equation (40), the output voltage, $${\mathrm{V}}_{\mathrm{o}}$$ is expressed as

The output voltage can be maintained within a desired range by choosing large $${\mathrm{K}}_{\mathrm{e}}$$ thus achieving good voltage regulation.

To speed up the dynamic response of power sharing, so that the input to an integrator becomes zero at the steady state, a proportional controller is added with it, as shown in Equation (43).

or equivalently, the time domain form of Equation (44) is expressed as

The following structure, shown in Figure 9 can be drawn by referring Equation (45).

The value of $${K}_{p}$$ is chosen carefully in order to get a stable response. In this study, the value of $${K}_{p}$$ is chosen 0.4 for the linear load and 0.1 for the nonlinear load.

With the exception of capacitive inverters, when the load is nonlinear, the THD_v is significant. The strategy of bypassing harmonic current components, shown in Figure 10, can be used to improve the quality of the output voltage. Generally speaking, nonlinear loads or/and pulse width modulation cause harmonic components in the current i (shown in Figure 3), which cause harmonic voltage drops in the output impedance, $${Z}_{o}$$. The output voltage quality degrades and causes high THD due to the appearance of harmonic voltage drops on the $${Z}_{o}$$. Therefore, rather than its type, the output impedance value has a significant impact on THD_v [7,12,13].

The output impedance of the inverter with this scheme is stated in Equation (46).

where,

The K_r(s) can be designed to have low gain at low frequency and high gain at high frequency to meet the requirements of power sharing and low output THD_v. This concept can be applied to all types of inverters. The following set of equations is written by referring to Figure 10.

where i_L = i + $$\frac{{\mathrm{K}}_{r}\left(s\right)}{{\mathrm{K}}_{i}}$$ $${\mathrm{v}}_{\mathrm{o}}$$

By referring Equation (51), it can be seen that the controller block of Figure 11 is equivalent to feedback current i_L = i + $$\frac{{\mathrm{K}}_{\mathrm{r}}\left(s\right)}{{\mathrm{K}}_{i}}$$ $${\mathrm{v}}_{\mathrm{o}}$$, which is the summation of current through the admittance branch connected across the output terminals and i. In other words, it can be inferred that the block diagram shown in Figure 10 is equivalent to the controller block shown in Figure 11. After careful investigation, it can be seen that structurally the principle is the same as that of proportional current feedback control to achieve a resistive type inverter, with the exception of an additional current component of $$\frac{{\mathrm{K}}_{\mathrm{r}}\left(s\right)}{{\mathrm{K}}_{i}}$$ $${\mathrm{v}}_{\mathrm{o}}$$ in inductor current, i_L. Filter capacitor C and admittance branch$$\frac{{\mathrm{K}}_{\mathrm{r}}\left(s\right)}{{\mathrm{K}}_{i}}$$ form a parallel connection. In simple words, the controller block diagram of Figure 3 is equivalent to adding $$\frac{{\mathrm{K}}_{\mathrm{r}}\left(s\right)}{{\mathrm{K}}_{i}}$$ with the filter capacitor, as shown in Figure 12.

There are parallel admittance branches corresponding to each harmonic frequency component. For example, if only two harmonic frequency components h = 3 and h = 5 are considered, then there will be a parallel combination of two admittance branches in the equivalent circuit diagram. Each branch is a series combination of resistance$$\frac{{\mathrm{K}}_{i}}{{\mathrm{K}}_{h}}$$, inductance $$\frac{{\mathrm{K}}_{i}}{2\xi h\omega {\mathrm{K}}_{h}}$$ and capacitance $$\frac{2\xi {\mathrm{K}}_{h}}{h\omega {\mathrm{K}}_{i}}$$, that resonates at the h-th harmonic frequency, i.e., hω. This is illustrated in Figure 13.

Where $${r}_{h}$$ = $$\frac{{\mathrm{K}}_{i}}{{\mathrm{K}}_{h}}$$, $${c}_{h}$$ = $$\frac{2\xi {\mathrm{K}}_{h}}{h\omega {\mathrm{K}}_{i}}$$, $${l}_{h}$$ = $$\frac{{\mathrm{K}}_{i}}{2\xi h\omega {\mathrm{K}}_{h}}$$

It is worthwhile to note that $$\frac{{\mathrm{K}}_{i}}{{\mathrm{K}}_{h}}$$ is the remaining impedance (referring Equation (53)) at the h-th harmonic frequency. For completely eliminating the h-th harmonic voltage component in the output voltage, $${\mathrm{K}}_{i}$$ should be zero because $${\mathrm{K}}_{h}$$ is finite. This means that the resistive output impedance of the inverter adds the harmonics in the output voltage. It is possible to reduce some harmonic voltage components through a trade-off when determining $${\mathrm{K}}_{i}$$.

In order to further improve the output voltage quality, the aforementioned strategy is modified. The modified strategy consists of multiple parallel circuits tuned to individual harmonic frequency components (h = 3, 5, 7, …, etc.) as shown in Figure 14.

Where $${i}_{L}$$ is the filter inductor current, i is the output current, and $${i}_{h}$$ (h = 3, 5, 7, ...) is the bypassed harmonic component of the current $${i}_{L}$$. The $${i}_{h}$$ is expressed as

where $${Y}_{h}$$ is admittance of h-th circuit, expressed in Equation (55).

The resonant frequency of the circuit tuned at h-th harmonic frequency is

Now, the inductor current $${i}_{L}$$ is

It is observed through Equation (55) that a circuit tuned at h-th harmonic frequency offers an infinite admittance path to the corresponding harmonic frequency current component, thereby bypassing it. In this way, the output voltage quality improves when harmonic current components bypass through tuned parallel circuits. Another way to look at this improvement is in terms of the output impedance of the inverter, which is derived as follows.

The following KVL equation can be written for the filter circuit of the inverter.

L is a filter inductor in units of henry; $${i}_{L}$$ is current through it and $${\mathrm{v}}_{\mathrm{o}}$$ is the output voltage.

The signal u, generated through the control strategy, is expressed as

where K_i is the virtual resistance; $${\mathrm{Y}}_{r}$$ is a virtual resonant admittance function; $${\mathrm{v}}_{\mathrm{r}}$$ is the reference voltage generated in the control scheme.

Upon equating signals in Equation (58) and Equation (59).

The output impedance is expressed in Equation (61).

The magnitude and phase plots of $${Z}_{o}$$ are shown in Figure 15.

The magnitude plot, shown in Figure 15a, reveals that the output impedance of the inverter at dominating harmonic frequencies (h = 3, 5, 7, 9, 11, 13, 15) is close to zero. Therefore, the voltage drop at these harmonic frequencies also tends to zero, thereby improving the quality of the output voltage. By carefully examining Equation (55), it is observed that the phase value near these frequencies may not acquire zero value if parameters are not tuned properly, leading to instability in the system. In order to overcome this, a small parasitic resistance $${r}_{par}$$ (≈0.1 Ω) is considered in series with $${L}_{h}.$$

With this consideration, the magnitude and phase plots are shown in Figure 15b. The admittance at h-th harmonic frequency is $$\frac{{R}_{h + }{r}_{par}}{{r}_{par} {R}_{h}}$$.

In this section, the small signal stability analysis for the inverter control system of capacitive inverter and resistive inverter (BHC strategy) is discussed [14].

The small signal stability analysis of the capacitive inverter system is described in the following subsection. Subsequently, the simulation results of various scenarios are discussed.

Small signal stability is conducted for one inverter participating in the parallel operation. Small disturbances around the phase angle (δ) and the inverter RMS voltage (E) are considered when linearizing Equation (31).$${V}_{o}$$ is the RMS output voltage across the load.

Linearizing controller Equations in Equation (34) yields

Normally, the powers (Active & Reactive) are measured through low pass filter of the form$$\frac{{\omega }_{f}}{s + {\omega }_{f}}$$. Considering this and using Equation (62), Equation (63), Equation (64) and Equation (65), a fourth order polynomial is formed in ‘s’ to investigate the stability (refer to Appendix A). It is evident from Figure 16a that the proposed strategy is stable for output impedance angle ranging from −$$\frac{\pi }{2}$$ to 0 radians.

Now, when proportional gain ($${K}_{p}$$) is added around an integrator in the voltage-active power loop, the following variables are chosen as states.

where $${E}_{ref}$$ and $${V}_{c}$$ are the RMS value of reference voltage and voltage across the virtual capacitor, respectively. The taylor expansion of the dynamic model, presented in Equation (66), Equation (67), Equation (68), Equation (69), Equation (70), Equation (71), Equation (72), Equation (73) and Equation (74) yields the small signal model with the following state space equation.

where,

The coefficients of the state space matrix, $${A}_{s}$$, are not expressed here due to the page limit. In order to access the effect of $${K}_{p}$$ on the system damping, the eigenvalues are computed for two cases as shown in Table 2 and Table 3 below.

In Table 2, two very slow decaying modes (7th: 1.190287144 × 10⁻¹³ and 8th: 0) are shown, which shift to the left side of the complex plane upon adding the proportional gain ($${K}_{p}$$) as shown in Table 3. If $${K}_{p}$$ increases beyond certain value, system will lose its stability. The traces of dominant eigenvalue with respect to increasing $${K}_{p}\,$$are shown in Figure 16b.

Further, a PF (participation factor) based analysis is conducted, illustrated in Table 4, to notice the participation of various states in a particular eigenvalue.

It is observed that there is a heavy dominance of states E and $${V}_{ref}$$ in eigenvalues 7th and 8th. Similarly, 4th eigenvalue is dominated by state $$\dot{P}$$. Eigenvalue pair-1,2 is dominated by states 5–8 primarily.

For a stable system, participation factor analysis provides the physical interpretation of the stable modes by identifying the dominant state variables associated with each eigenvalue. This enables classification of the system dynamics and indicates the controller states whose parameters are the most effective for improving damping or modifying dynamic performance, even when all eigenvalues lie in the left-half of the complex plane.

The inductor current, as stated in Equation (78), is the sum of the currents through the load and the filter capacitor.

where $${r}$$ is the equivalent series resistor of the filter capacitor. The Equation (78) can also be written as in Equation (79).

$${Z}_{eqv}$$ is the equivalent impedance of the parallel combination of the filter capacitor and the load as shown in Figure 17a. If load Z_L is passive, then it must be a positive real function, the equivalent impedance $${Z}_{eqv}$$ is stable for any passive $${Z}_{L}$$ as Nyquist plot of open loop transfer function $$\frac{1}{{Z}_{L}}\frac{srC + 1}{sC}$$, shown in Figure 17b, does not encircle the critical point (−1,0) on the s plane. It is noticeable that the presence of equivalent series resistance $$r$$ guarantees the system stability as it suppresses the oscillations. The stability of the closed loop transfer function can be judged by drawing the nyquist diagram of function M(s), described in Equation (80). However, if the controller is implemented digitally, the open loop transfer function is modified to $$\frac{\left(1 + {\mathrm{K}}_{\mathrm{r}}\left(\mathrm{s}\right){e}^{-{T}_{s}s}\right)}{sL + {K}_{i}{e}^{-{T}_{s}s}}$$ $${Z}_{eqv}$$, where $${T}_{s}$$ is the sampling period. Now, the proportional gain has to follow the inequality $${K}_{i} < \frac{\pi }{2}$$ $$\frac{\mathrm{L}}{{T}_{s}}$$ for ensuring the system stability.

where,

and,

The finite parameter $${\mathrm{K}}_{\mathrm{h}}\,$$in the controller can be determined by using the stability condition of small gain theorem. According to this theorem, system is stable if $${\| \frac{1 + {K}_{R}\left(s\right)}{sL + {K}_{i}}{Z}_{eqv}\| }_{ꝏ}$$ < 1, where $${\| \frac{1\mathrm{ }+ {K}_{R}\left(s\right)}{sL + {K}_{i}}{Z}_{eqv}\| }_{ꝏ}$$ is the maximum amplitude of open loop transfer function M(s).

In order to determine the upper limit of $${\mathrm{K}}_{3}$$, bode plots of M(s) are drawn in Figure 18 for $${\mathrm{K}}_{3}$$ = 15, 40, and 65, respectively. By careful observation of these plots, it is revealed that the system is stable for $${\mathrm{K}}_{3}$$ = 15 as peak magnitude is less than 1 in linear scale, whereas it approaches 1 for $${\mathrm{K}}_{3}$$ ≈ 40. The system is not stable for $${\mathrm{K}}_{3}$$ = 65 as peak magnitude is more than 1. Therefore, the upper limit for $${\mathrm{K}}_{3}$$ is determined by using the stability criteria of small gain theorem. Similarly, the safe operating limits for $${\mathrm{K}}_{5}$$ and $${\mathrm{K}}_{7}$$ can also be determined.

The real and reactive power, shown in Figure 19a, supplied by an individual inverter k, are stated in Equation (84) and Equation (85) [7,10,11,13,14].

Due to feedback resistive block, output impedance of inverter is dominantly resistive. Under this condition, $${Z}_{ok}$$ = $${R}_{ok}$$,

Therefore, the CDC for resistive inverter takes the form

where,

$${E}_{refk}$$: magnitude of reference voltage (volt) of k-th inverter

δ: phase angle of the reference voltage (radians)

$$|{Z}_{ok}|$$: magnitude of $${Z}_{ok}\mathrm{ }$$(≈$${R}_{ok}$$) (Ω)

θ: angle of $${Z}_{o}$$ (radians)

S, P and Q: apparent, real and reactive power (VA, W and VAr)

i: current flowing through $${Z}_{o}$$($${R}_{o}+j {X}_{o}$$) (amp)

$${V}_{o}$$: voltage of output terminals (volt)

$${E}^{*}$$ and $${\omega }^{*}$$ are nominal voltage and frequency of the system.

$${\mathrm{n}}_{k}$$ and $${\mathrm{m}}_{k}$$ are droop coefficients, which are computed through voltage drop ratio ($$\frac{{n}_{k}{P}_{k}}{{\mathrm{E}}^{\mathrm{*}}\mathrm{ }{\mathrm{K}}_{\mathrm{e}}}$$) and frequency boost ratio ($$\frac{{m}_{k}{Q}_{k}}{{\omega }^{\mathrm{*}}\mathrm{ }}$$) respectively.

Referring Equation (84) and Equation (86), the expression of active power of inverter k is expressed as

By referring Equation (86) and Equation (87), the deviation of voltage amplitude (ΔE) between two inverters is expressed in Equation (88).

The deviation in the voltage between two units lead to a significant error in power distribution. Therefore, in order for $${n}_{1}{P}_{1}$$ = $${n}_{2}{P}_{2}$$ to hold, ΔE should be zero. However, this condition is not fulfilled in practicality. It is fulfilled if

Therefore, for achieving accurate active power sharing, resistive output impedances ($${R}_{ok}$$, k = 1, 2) of two inverters should be designed to satisfy

Referring to Equation (90), it is clear that the p.u. output impedances of inverters must be the same in order to achieve accurate real power sharing. This is the foundation of the virtual impedance method. However, in practicality, there are challenges to achieve [7].

In steady state operation of inverters, accuracy of reactive power sharing is guaranteed under the condition $${\omega }_{1}$$ = $${\omega }_{2}$$. This is equivalent to

Alternatively, $${m}_{1}\frac{{E}_{ref1}{V}_{o}}{{R}_{01}}$$ sin$${\delta }_{1}$$= $${m}_{2}\frac{{E}_{ref2}{V}_{o}}{{R}_{o2}}$$ sin$${\delta }_{2}$$

Under the condition of $${\delta }_{1}$$ = $${\delta }_{2}$$ and $${E}_{ref1}$$ = $${E}_{ref2}$$

The above analysis concludes that $${n}_{k}$$ & $${m}_{k}$$ are related to accurate proportional power sharing in the conventional droop controller. In practicality, it is difficult to achieve the same per unit output impedance for inverters participating in the parallel operation. Other than this, disturbance, noise, and drift in parameters also limit proportionate power sharing. The concept of robust droop control, discussed in the next subsection, can be used to address this issue.

The Physical implementation of single phase inverter with its control loop is shown in Figure 3. In the inverter control loop, the feedback integrator block is replaced by a pure resistance (also called a virtual resistor) while implementing the BHC strategy. The 1-Փ resistive inverter, equipped with RDC scheme, is shown in Figure 19b, to achieve proportional power sharing [11]. The RMS value of the output voltage is compared with the nominal system voltage, and this difference is amplified by a gain to produce a signal that is summed up in the power-voltage loop. An idea behind bolting a regulator loop needs to be understood for proportional power sharing. The voltage-power droop, expressed in Equation (86), can also be stated as follows

Now,

Equation (94) works well for the grid-tied mode, where $$\mathrm{\Delta }{E}_{k}$$ must be zero as set power is sent to the grid without any error [11]. On the other hand, in off-grid mode, active power depends on the connected load and therefore $$\mathrm{\Delta }{E}_{k}$$ may not be zero. It also means that controller has to be different for two different operating modes. However, to avoid this, the principle of basic control theory can be used, where ($${E}^{*}{ - V}_{o}$$) is amplified and added to Δ$${E}_{k}$$ as shown in Figure 19b. This scheme is immune to computational errors, noise, and even disturbances. Additionally, this is a robust structure with respect to parameter drifts and component mismatches.

At the steady state, in power-voltage (P-E) loop, input to the integrator is zero.

If $${\mathrm{K}}_{\mathrm{e}}$$ is same for all inverters that are operating in parallel, the accurate reactive power sharing is guaranteed in proportion to the power rating of the inverters. Hence,

Equation (96) justifies an accurate active power sharing without the need for the same reference voltages. Moreover, the sharing of power need not necessarily depend on feeder impedances.

By referring Equation (95), $${V}_{o}$$ is expressed as

where $$\frac{{n}_{k}{P}_{k}}{{E}^{*}\mathrm{ }{K}_{{e}}}$$ is the voltage drop ratio. $${m}_{k}$$ and $${n}_{k}$$ are computed via frequency boost ratio ($$\frac{{m}_{k}{\mathrm{Q}}_{k}}{{\omega }^{\mathrm{*}}}$$) and voltage drop ratio, respectively.

Without bolting the regulator on the control loop of the inverter, the proportional power sharing between parallel inverters can not be guaranteed until the p.u. output impedances of inverter units are the same.

In the RDC model of inverter, the voltage drop ratio is smaller than the drop ratio due to load and/or droop component. On the other hand, the conventional droop controller includes the voltage drop ratio due to the droop component only and does not include the voltage drop ratio of the load component. Therefore, the discussed RDC scheme compensates for the voltage drop ratio due to load as well as the droop component and provides good capability of voltage regulation. According to Equation (97), the voltage drop ratio depends on $${n}_{i}$$, $${P}_{i}$$ and $${\mathrm{K}}_{\mathrm{e}}$$. Large $${\mathrm{K}}_{\mathrm{e}}$$ enables a much smaller voltage drop ratio. However, if the voltage measurement is erroneous, the trade off between power sharing accuracy and voltage drop must be made as the voltage drop is proportional to $$\frac{{n}_{i}}{{\mathrm{K}}_{\mathrm{e}}}$$ and power sharing error is inversely proportional to $$\frac{{n}_{i}}{{\mathrm{K}}_{\mathrm{e}}}.$$ For an example, if an error in voltage measurement ($$\frac{{\mathrm{\Delta }V}_{o}}{{E}^{*}}$$), which may be due to inaccurate sensor measurement, is 0.1% at the rated power and drop ratio $$(\frac{n_iP_i}{\mathrm{E}^*\mathrm{~K}_\mathrm{e}})$$ is $$5%$$, the error in active power sharing becomes $$\frac{0.1}{5}$$ = 2%, that is quite reasonable.

The deviation of output voltage from its nominal value is shown in Table 5, for capacitive and BHC assisted inverter.

There is a further need of development in $${Z}_{o}$$. This can be understood by taking an example of integral control assisted inverter. When it comes to the significant voltage harmonics at low frequencies, the overall output impedance is essentially the same as the output impedance without taking the filter capacitor into account. The ideal virtual capacitor $${C}_{o}$$ is therefore largely unaffected by the filter capacitor. However, further research is required to investigate the impact of the filter capacitor on the overall performance of the inverter system.

By referring Figure 3 [12]

Also,

Therefore,

where i is summation of output current ($${i}_{o}$$) and current through filter capacitor branch ($${i}_{f} = \frac{{\mathrm{V}}_{\mathrm{o}}}{\frac{1}{sC} + {r}_{esr}}$$).

Therefore,

where,

At low frequencies,

Normally, at the fundamental frequency, C << $${C}_{o}$$

This means that C and $${r}_{esr}$$ have negligible impact on the output voltage at the fundamental frequency. Let us examine the effect of filter capacitor for the third harmonic voltage component. It is evident that when C increases, the phase curve shifts to the left and the top of the magnitude curve shifts to the left-bottom (see Figure 20). If there are some harmonic components in the reference voltage $${v}_{r}$$, it suggests that the filter capacitor affects voltage harmonics. The phase curve becomes smoother and the peak falls significantly as r and $${r}_{esr}$$ increases.

The virtual resistor can be added to the virtual resonant impedance to prevent energy loss brought on by the real resistor. On the one hand, the virtual resistor would increase the magnitude of voltage harmonic components throughout a broad frequency range. Conversely, it might reduce the magnitude of voltage harmonic components at the resonant frequencies of virtual resonant impedance. Additionally, the virtual resistor gives the system better stability and damping. Then, it is necessary to research how to carefully design parameters to reduce THD_v while retaining good damping.

Incorporating smartness in the output impedance is an another way to think in this direction. To overcome the limitations of tuned filters, smart impedance enables the removal of the need for tuning procedures and performs multiple-frequency harmonic mitigation electronically, etc. [20].

A system of two single phase capacitive inverters operating in parallel is simulated for 10 s to verify the design. Matlab Simulink R2025b software is used to carry out simulations on the system with processor Intel (R) Core (TM) i5-8365U CPU @ 1.60GHz 1.90 GHz and 8 GB ram. Initially, inverter 1 (50 VA) and inverter 2 (25 VA) are operated in parallel to supply a linear load (R = 9 $$\mathrm{\Omega }$$). At t = 4.5 s, inverter 2 (25 VA) stops operating, and inverter 1 (50 VA) alone shares the connected load. Detailed simulation parameters are given in Table 6.

Time domain responses are shown in Figure 16. By referring Figure 21a, it is evident that both inverters share power (P) in the ratio of 1:2 ($$\frac{5.26}{10.53} \approx \frac{1}{2}$$) during parallel operation. In the same time interval, reactive power (Q) also settles in the ratio of 1:2 ($$\frac{-0.6567}{-1.312} \approx \frac{1}{2}$$). Inverter current and voltages are shown in Figure 21c–f.

The total load power is $$\frac{{E}^{*2}}{{R}_{L}}$$ = $$\frac{144}{9}$$ = 16 Watt. The total power shared, when both INV1 and INV2 are operational, is 10.53 + 5.26 ≈ 15.8 Watt which is very close to 16 Watt.

One more similar inverter 3, which has VA rating one third of inverter 1, is added. The reactive power-voltage and active power-frequency coefficients (n_c3, m_c3), calculated from the voltage drop/boost ratio and the frequency drop/boost ratio respectively, are three times those of inverter 1. When all three inverters operate in parallel, at the steady state, the power sharing ratio between inverter-1 and inverter-2 is 2:1 ($$\frac{10.79}{5.384} \approx \frac{2}{1}$$), between inverter-1 and inverter-3 is 3:1 ($$\frac{10.79}{3.603} \approx \frac{3}{1}$$). The RMS output voltage, output voltage, output current, and inductor current are shown in Figure 24c–g, respectively. In Figure 24d,e, waveforms $${\mathrm{v}}_{\mathrm{o}1}$$, $${\mathrm{v}}_{\mathrm{o}2}$$ and $${\mathrm{v}}_{\mathrm{o}3}$$ appear identical, as expected, since they are measured at the common output terminals.

The BHC strategy is applied to reduce THD_v in case of nonlinear load-1, connected to two parallel operating inverters. Further, the modified BHC approach is tested for nonlinear load-2 (single phase rectifier followed by regulated buck converter), shown in Figure 20b, to prove its effectiveness.

A system of two single phase resistive inverters operating in parallel is simulated for 15 s to verify the design. The robust droop control structure is adopted for proportional power sharing as shown in Figure 8, in which resistive droop control equations are used. The droop coefficients are m_iR, n_iR and K_e is constant. E^* and ω^* are the rated voltage and frequency of the system. Initially, inverter-1 (50 VA) and inverter-2 (25 VA) are operated in parallel to supply a nonlinear load-1, Z_L (full bridge rectifier with LC filter, L_NL = 150 μH and C_NL= 1000 μF, R_NL = 9 Ω). At t = 7.5 s, inverter-1 (50 VA) is disconnected, and load is shared by inverter-2 only. The parameters are given in the Table A1 (see Appendix A). The simulation results are shown in Figure 25.

The instantaneous output voltage and THD_v with further development of BHC strategy are shown in Figure 26. The quality of output voltage improves to much better extent.

It is important to observe from the FFT analysis that the total harmonic distortion of the output voltage with the BHC strategy is improved significantly. It is reduced to 5%, which was 15–20% in the case of capacitive inverters. Therefore, the BHC strategy with robust droop control supersedes the strategy of capacitive inverters. The active and reactive power sharing for all discussed cases has been shown in Table 7. The BHC strategy is developed further to enhance the quality of output that led THD_v to 2.85%, recommended by IEEE-519 standard. The individual harmonic content in the output voltage (fundamental, h₃, h₅, …, etc.) has been listed in Table 8. Subsequently, Table 9 shows the comparison among four methods (BHC, modified BHC, capacitive inverter, and HDC). Among all, modified BHC outperforms in mitigating THD_v in the case of highly nonlinear loads.

The effectiveness of modified BHC is evaluated in case of nonlinear load case-2. The active and reactive power sharing responses are illustrated in Figure 27a,b, respectively, followed by FFT analyses performed with and without the modified BHC strategy.

Note: While applying modified BHC in case of nonlinear load-2, the ratings of two inverters have been interchanged (now INV1-25 VA, INV2-50 VA). The approach effectively reduces the THD_v from 19% (without equipping the strategy) to 1% (with equipping the strategy). Detailed simulation parameters are given in Table A1.

In this paper, an analytical approach is followed to design an integral controller parameter for 1-Փ inverter in order to achieve the objective of reduced total harmonic distortion in the output voltage. Its optimum design is ensured to reduce THD in the output voltage as well as proportional power sharing to the load. The drawbacks of conventional droop control and its remedial measures are highlighted by incorporating the robust droop control as far as parallel operation of two inverters is concerned. The replacement of an integrator by a PI controller in the PV (active power-voltage) loop is discussed to derive the new possible structure. The small signal stability analysis ensures the stable operation for a certain output impedance angle range. Subsequently, the state space matrix is formed, and eigenvalue/PF analysis is done to identify the dominant state variables. The power sharing ratio of two/three parallel operated inverters is calculated for a test example (both for linear and nonlinear loads) through time domain simulation. Further, the BHC strategy and its modified form, equipped with robust droop control is discussed to enhance the voltage quality for a nonlinear load. The time domain simulation result proves its superiority over the capacitive inverter in terms of %THD of the output voltage. Application of the controllers can be extended to grid connected and three phase inverters. Additionally, the discussion is likely to be extended experimentally by hardware-in-the-loop testing setups in the future.

A polynomial in ‘s’ is formed by substituting ΔE(s) in Equation (A1). ‘s’ is laplace operator.

where A, B, C, D and E are functions of inverter output impedance angle.

The authors express their sincere gratitude to the Department of Electrical Engineering, NIT Delhi, NIT Uttrakhand, for providing the facilities and research environment necessary for conducting this study. The authors also thank all individuals who directly or indirectly contributed to the successful completion of this study.

The details of the individual and collective contributions are presented as follows: Conceptualization, S.B.; Methodology, S.B.; Software, S.B.; Writing—Original Draft Preparation, S.B.; Writing—Review & Editing, V.S. and M.K.; Supervision, V.S. and M.K.; Funding Acquisition, Not Applicable.

Not applicable.

Not applicable.

The data, supporting the findings of this study are available from the corresponding author upon reasonable request.

No funding has been received to carry out the written draft of the manuscript.

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.